1. Field of the Invention
Methods and apparatuses consistent with the present invention relate to mapping of a memory, and more particularly, to memory mapping having improved both bus utilization efficiency and memory channel utilization efficiency.
2. Description of the Related Art
A decoder used in a high definition (HD) video environment frequently has to access an external memory, and thus the bus utilization efficiency of the decoder has to be improved for more efficient real time processing.
FIG. 1 is a block diagram of a related art multi-format decoder. Referring to FIG. 1, the related art multi-format decoder includes a syntax processor SP, a transform processor TP and a motion vector processor MP. Detailed structures and operations of these processors are well known in the art, thus detailed explanations thereof are omitted.
The motion vector processor MP which performs inter-motion compensation or loop filtering reads a large quantity of data from external memories M0 and M1 through buses, and writes a large quantity of data to the external memories M0 and M1. Accordingly, the external memory access time of the motion vector processor MP is an important factor for determining the entire processing time of the multi-format decoder. Specifically, an inter read module (not shown) of the motion vector processor MP reads reference data stored in the memories M0 and M1. Thus, in order to reduce the processing time of the multi-format decoder, it is very important to improve bus utilization efficiency and memory channel utilization efficiency between the inter-read module and the memories M0 and M1.
FIG. 2 illustrates the structures of related art memories M0 and M1 including a plurality of banks. Referring to FIG. 2, each of the memories M0 and M1 include four banks. A currently used general memory includes four banks, but a memory having eight banks has been developed. Dividing a memory into a plurality of banks enables overlapping of a command transmission period in which data addresses are transmitted, and a data transmission period in which data is transmitted when the data is written in (or read from) different banks. Accordingly, bank utilization efficiency can be improved through bank interleaving. This will be explained in more detail with reference to FIGS. 3A and 3B.
FIG. 3A illustrates operation timing when bank interleaving does not occur and FIG. 3B illustrates operation timing when bank interleaving occurs. Referring to FIG. 3A, when data is written in (or read from) a bank, a command transmission period is inserted between data transmission periods when the data is continuously written (or read). In this case, the command transmission period functions as a gap between the data transmission periods, which results in a decrease in bus utilization efficiency.
Referring to FIG. 3B, when data is written in (or read from) two banks, the data transmission period of the first bank and the command transmission period of the second bank can be overlapped with each other and the command transmission period of the first bank and the data transmission period of the second bank can be overlapped with each other even when the data is continuously written (or read). Consequently, bank interleaving occurs between the banks to eliminate a gap between the data transmission periods. This enables continuous data transmission to improve bus utilization efficiency.
FIGS. 4A, 4B, and 4C illustrate an operation of a motion vector processor MP to motion-compensate block data of a video frame in a frame mode or a field mode. FIG. 4A illustrates the motion vector processor MP and the memories M0 and M1 connected to the motion vector processor MP through buses, FIG. 4B illustrates the block data composed of a plurality of lines 0, 1, 2, 3, . . . in the video frame, and FIG. 4C illustrates a related art memory mapping format in which the lines constructing the block data are written in the two memories M0 and M1.
Referring to FIG. 4C, even-numbered lines 0, 2, 4, 6, 8, 10, 12, 14, . . . among the lines constructing the block data are written in the memory M0 and odd-numbered lines 1, 3, 5, 7, 9, 11, 13, 15, . . . are written in the memory M1. Accordingly, only the even-numbered lines 0, 2, 4, 6, 8, 10, 12, 14, . . . are written (or read) via the bus between the motion vector processor MP and the memory M0 of FIG. 4A and only odd-numbered lines 1, 3, 5, 7, 9, 11, 13, 15, . . . are written (or read) via the bus between the motion vector processor MP and the memory M1.
When motion compensation is carried out in the field mode, however, only the even-numbered lines or odd-numbered lines are accessed. Thus, the bus between the motion vector processor MP and the memory M1 is not utilized when only the even-numbered lines are accessed and the bus between the motion vector processor MP and the memory M0 is not utilized when only the odd-numbered lines are accessed. Accordingly, memory channel utilization efficiency is deteriorated.